Porting of finite element integration algorithm to Xeon Phi coprocessor-based HPC architectures
Authors:
- Filip Krużel,
- Krzysztof Banaś,
- Mauro Iacono
Abstract
In the present article, we describe the implementation of the finite element numerical integration algorithm for the Xeon Phi coprocessor. The coprocessor was an extension of the many-core specialized unit for calculations, and its performance was comparable with the corresponding GPUs. Its main advantages were the built-in 512-bit vector registers and the ease of transferring existing codes from traditional x86 architectures. In the article, we move the code developed for a standard CPU to the coprocessor. We compare its performance with our OpenCL implementation of the numerical integration algorithm, previously developed for GPUs. The GPU code is tuned to fit into a coprocessor by our auto-tuning mechanism. Tests included two types of tasks to solve, using two types of approximation and two types of elements. The obtained timing results allow comparing the performance of highly optimized CPU and GPU codes with a Xeon Phi coprocessor performance. This article answers whether such massively parallel architectures perform better using the CPU or GPU programming method. Furthermore, we have compared the Xeon Phi architecture and the latest available Intel’s i9 13900K CPU when writing this article. This comparison determines if the old Xeon Phi architecture remains competitive in today’s computing landscape. Our findings provide valuable insights for selecting the most suitable hardware for numerical computations and the appropriate algorithmic design.
- Record ID
- CUT3599af9176c149adb5bea74451897d64
- Publication categories
- ;
- Author
- Journal series
- Computer Assisted Methods in Engineering and Science, ISSN 2299-3649
- Issue year
- 2023
- Vol
- 30
- No
- 4
- Pages
- 427-459
- Other elements of collation
- rys.; tab.; wykr.; Bibliografia (na s.) - 456-459; Bibliografia (liczba pozycji) - 51; Oznaczenie streszczenia - Streszcz. ang.; Data udostępnienia on-line - 2023-08-29; Numeracja w czasopiśmie - Vol. 30, No. 4
- Keywords in English
- CPU, optimization, parallelization, vectorization, Intel Xeon Phi
- DOI
- DOI:10.24423/cames.578 Opening in a new tab
- URL
- https://cames.ippt.pan.pl/index.php/cames/article/view/578 Opening in a new tab
- Language
- eng (en) English
- License
- Score (nominal)
- 70
- Score source
- journalList
- Score
- Uniform Resource Identifier
- https://cris.pk.edu.pl/info/article/CUT3599af9176c149adb5bea74451897d64/
- URN
urn:pkr-prod:CUT3599af9176c149adb5bea74451897d64
* presented citation count is obtained through Internet information analysis, and it is close to the number calculated by the Publish or PerishOpening in a new tab system.