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Digital data conversion using content addressable memory
Authors:
- Zbigniew Kokosiński
Abstract
In this paper a novel digital data conversion scheme is proposed that may be applied in analog or digital data acquisition systems. In this scheme possible input redundancy of combinational logic circuit is eliminated by argument reduction. CAM (associative memory) is used in two implementations - for binary and ternary logic, respectively. For binary CAM hardware generators of column masks may be applied. The resulting digital structure can be easily implemented in FPGA.
- Record ID
- CUT86fc506e40734e27821c9e7b58ebfd7c
- Publication categories
- ; ;
- Author
- Pages
- 680-684
- Other elements of collation
- schem.; Bibliografia (na s.) - 684; Bibliografia (liczba pozycji) - 23; Oznaczenie streszczenia - Abstr.
- Book
- IDAACS' 2019 : proceedings of the 2019 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS). Vol. 2, 2019, [Piscataway], Institute of Electrical and Electronics Engineers, IEEE, ISBN 978-1-7281-4069-8 (electronic)
- Keywords in English
- CAM, combinational circuit, data convertion, DRMAX-DC algorithm, mask generator, Minimum Base Problem
- DOI
- DOI:10.1109/IDAACS.2019.8924304 Opening in a new tab
- URL
- https://ieeexplore.ieee.org/document/8924304 Opening in a new tab
- Related project
- Innowacyjne systemy automatyki. . Project leader at PK: , ,
Działalność statutowa - Language
- eng (en) English
- Score (nominal)
- 20
- Additional fields
- Indeksowana w: Web of Science, Scopus
- Uniform Resource Identifier
- https://cris.pk.edu.pl/info/article/CUT86fc506e40734e27821c9e7b58ebfd7c/
- URN
urn:pkr-prod:CUT86fc506e40734e27821c9e7b58ebfd7c
* presented citation count is obtained through Internet information analysis, and it is close to the number calculated by the Publish or PerishOpening in a new tab system.